Relationship between co-packaged optics and chips

Co-packaged optics (CPO) integrates optical components directly with electronic chips, reducing distance between photonics and electronics to enhance bandwidth, performance, and power efficiency.

Co-packaged optics (CPO) is a packaging approach where optical components, such as lasers and photodetectors, are integrated alongside electronic chips like ASICs or GPUs within the same package . This integration minimizes the physical distance between the optical and electrical components, which reduces signal loss, lowers latency, and increases data throughput compared to traditional pluggable optics or copper interconnects . Essentially, CPO brings fiber directly to the chip, enabling high-density optical I/O and scalable connectivity for data centers and AI clusters .

CPO relies on heterogeneous integration of photonic integrated circuits (PICs) and electronic integrated circuits (EICs) on a single substrate . Common approaches include:

• Silicon interposers or bridges (e.g., Intel EMIB) to co-locate the core die and EICs.
• 3D stacking of PICs on top of EICs or placing them side-by-side on organic substrates.
• Advanced packaging technologies like TSMC's CoWoS and CoWoS-L to enhance interconnect density and thermal management .

These methods aim to shorten electrical links between the chip and optical engine, improving signal integrity and enabling multiple optical chiplets to be placed closer to the main die .

1. Power Efficiency: By reducing the distance between optics and electronics, CPO lowers energy loss and overall power consumption, which is critical in hyperscale data centers .
2. High Bandwidth: Direct integration supports higher data rates and throughput, essential for AI, HPC, and cloud-scale workloads .
3. Performance: Enhanced signal integrity, reduced insertion loss, and lower latency improve overall system performance .
4. Scalability: CPO allows dense fiber routing and modular expansion, supporting large-scale AI and data center architectures .

• Thermal Management: Co-locating high-power EICs and PICs increases heat density, requiring advanced cooling solutions .
• Cost and Complexity: Large interposers and 3D stacking add manufacturing complexity and cost .
• Interoperability: Standardization and serviceability can be challenging, as all ports in a CPO system typically use the same optics type .

CPO represents a shift from pluggable and on-board optics toward tightly integrated optical-electronic packages to overcome the limitations of copper interconnects at high speeds . Emerging solutions, such as glass substrates, offer improved thermal, mechanical, and interconnect properties, enabling further scaling of transistors and optical integration beyond 2030 .

In summary, the relationship between co-packaged optics and chips is one of direct integration, where optical engines are brought into close proximity with electronic dies to achieve higher bandwidth, lower latency, and improved power efficiency, making CPO a critical technology for next-generation computing and data center infrastructure.